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» A Higher-Level Language for Hardware Synthesis
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SASP
2008
IEEE
183views Hardware» more  SASP 2008»
15 years 4 months ago
Application Acceleration with the Explicitly Parallel Operations System - the EPOS Processor
Different approaches have been proposed over the years for automatically transforming High-Level-Languages (HLL) descriptions of applications into custom hardware implementations. ...
Alexandros Papakonstantinou, Deming Chen, Wen-mei ...
DAGSTUHL
2004
14 years 11 months ago
Removing Cycles in Esterel Programs
Abstract. Synchronous programs may contain cyclic signal interdependencies. This prohibits a static scheduling, which limits the choice of available compilation techniques for such...
Jan Lukoschus, Reinhard von Hanxleden
CODES
2006
IEEE
15 years 3 months ago
Generic netlist representation for system and PE level design exploration
Designer productivity and design predictability are vital factors for successful embedded system design. Shrinking time-to-market and increasing complexity of these systems requir...
Bita Gorjiara, Mehrdad Reshadi, Pramod Chandraiah,...
DSD
2007
IEEE
120views Hardware» more  DSD 2007»
15 years 4 months ago
Cotransformation Provides Area and Accuracy Improvement in an HDL Library for LNS Subtraction
The reduction of the cumbersome operations of multiplication, division, and powering to addition, subtraction and multiplication is what makes the Logarithmic Number System (LNS) ...
Panagiotis D. Vouzis, Sylvain Collange, Mark G. Ar...
MICRO
1994
IEEE
85views Hardware» more  MICRO 1994»
15 years 1 months ago
A high-performance microarchitecture with hardware-programmable functional units
This paper explores a novel way to incorporate hardware-programmable resources into a processor microarchitecture to improve the performance of general-purpose applications. Throu...
Rahul Razdan, Michael D. Smith