145 search results - page 7 / 29 » A Higher-Level Language for Hardware Synthesis |
ARC
2008
Springer
14 years 11 months ago
2008
Springer
Abstract. In this paper, we present the PARO design tool for the automated hardware synthesis of massively parallel embedded architectures for given dataflow dominant applications....
DATE
2005
IEEE
15 years 3 months ago
2005
IEEE
A class of discrete event synthesis problems can be reduced to solving language equations F • X ⊆ S, where F is the fixed component and S the specification. Sequential synthes...
ASPDAC
2007
ACM
15 years 1 months ago
2007
ACM
In this paper, we present a method for generating checker circuits from sequential-extended regular expressions (SEREs). Such sequences form the core of increasingly-used Assertion...
DATE
1999
IEEE
15 years 1 months ago
1999
IEEE
Previous work has shown that sizable power reductions can be achieved by shutting down a system's sub-circuits when they are not needed. However, these shutdown techniques fo...
FDL
2005
IEEE
15 years 3 months ago
2005
IEEE
Although Moore’s Law enables a huge number of components to be integrated into a single chip, design methods that will allow system architects to put the components together to ...