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» A Higher-Level Language for Hardware Synthesis
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VLSID
2005
IEEE
140views VLSI» more  VLSID 2005»
15 years 10 months ago
Variable Resizing for Area Improvement in Behavioral Synthesis
High level synthesis tools transform an algorithmic description to a register transfer language (RTL) description of the hardware. The algorithm behavior is typically described in...
R. Gopalakrishnan, Rajat Moona
CAV
2010
Springer
214views Hardware» more  CAV 2010»
15 years 1 months ago
Comfusy: A Tool for Complete Functional Synthesis
Synthesis of program fragments from specifications can make programs easier to write and easier to reason about. We present Comfusy, a tool that extends the compiler for the gener...
Viktor Kuncak, Mikaël Mayer, Ruzica Piskac, P...
FCCM
1995
IEEE
135views VLSI» more  FCCM 1995»
15 years 1 months ago
Architectural descriptions for FPGA circuits
FPGA-based synthesis tools require information about behaviour and architectural to make effective use of the limited number of cells typically available. A hardware description l...
Satnam Singh
ACSD
2008
IEEE
135views Hardware» more  ACSD 2008»
14 years 11 months ago
Synthesis of Petri nets from infinite partial languages
In this paper we present an algorithm to synthesize a finite unlabeled place/transition Petri net (p/t-net) from a possibly infinite partial language, which is given by a term ove...
Robin Bergenthum, Jörg Desel, Robert Lorenz, ...
FPL
2009
Springer
115views Hardware» more  FPL 2009»
15 years 2 months ago
Recursion in reconfigurable computing: A survey of implementation approaches
Reconfigurable systems are widely used nowadays to increase performance of computationally intensive applications. There exist a lot of synthesis tools that automatically generate...
Iouliia Skliarova, Valery Sklyarov