110 search results - page 3 / 22 » A Highly-Configurable Cache Architecture for Embedded System... |
DATE
2004
IEEE
13 years 10 months ago
2004
IEEE
DATE
1999
IEEE
13 years 10 months ago
1999
IEEE
This paper proposes a methodology to evaluate the effects of encodings on the power consumption of system-level buses in the presence of multi-level cache memories. The proposed m...
ICCAD
2002
IEEE
14 years 3 months ago
2002
IEEE
Embedded system programs tend to spend much time in small loops. Introducing a very small loop cache into the instruction memory hierarchy has thus been shown to substantially red...
DAC
2008
ACM
14 years 7 months ago
2008
ACM
We present a cross-layer customization methodology for latency and bandwidth efficient inter-core communication in embedded multiprocessors. The methodology integrates compiler, o...
DAC
1998
ACM
14 years 7 months ago
1998
ACM
Memory is one of the most restricted resources in many modern embedded systems. Code compression can provide substantial savings in terms of size. In a compressed code CPU, a cach...