42 search results - page 2 / 9 » A Hybrid Analog-Digital Routing Network for NoC Dynamic Rout... |
AHS
2006
IEEE
14 years 12 days ago
2006
IEEE
This paper describes the architecture of our dynamically reconfigurable Network-on-Chip (NoC) architecture that has been proposed for reconfigurable Multiprocessor system-on-chip ...
ISCAS
2007
IEEE
14 years 18 days ago
2007
IEEE
— With increasing reliability concerns for current and next generation VLSI technologies, fault-tolerance is fast becoming an integral part of system-on-chip (SoC) and multicore ...
IPPS
2005
IEEE
13 years 12 months ago
2005
IEEE
On-line routing strategies for communication in a dynamic network on chip (DyNoC) environment are presented. The DyNoC has been presented as a medium supporting communication amon...
DAC
2006
ACM
14 years 9 days ago
2006
ACM
A novel routing algorithm, namely dynamic XY (DyXY) routing, is proposed for NoCs to provide adaptive routing and ensure deadlock-free and livelock-free routing at the same time. ...
DAC
2008
ACM
14 years 7 months ago
2008
ACM
In this paper we present a reconfigurable routing algorithm for a 2D-Mesh Network-on-Chip (NoC) dedicated to faulttolerant, Massively Parallel Multi-Processors Systems on Chip (MP...