19 search results - page 3 / 4 » A Large, Fast Instruction Window for Tolerating Cache Misses |
ISCA
2008
IEEE
15 years 6 months ago
2008
IEEE
Multicore processors have emerged as a powerful platform on which to efficiently exploit thread-level parallelism (TLP). However, due to Amdahl’s Law, such designs will be incr...
MICRO
1998
IEEE
15 years 3 months ago
1998
IEEE
This paper provides quantitative measurements of load latency tolerance in a dynamically scheduled processor. To determine the latency tolerance of each memory load operation, our...
125
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MICRO
1999
IEEE
15 years 3 months ago
1999
IEEE
Current microprocessors incorporate techniques to exploit instruction-level parallelism (ILP). However, previous work has shown that these ILP techniques are less effective in rem...
ISPASS
2010
IEEE
15 years 6 months ago
2010
IEEE
—The ongoing move to chip multiprocessors (CMPs) permits greater sharing of last-level cache by processor cores but this sharing aggravates the cache contention problem, potentia...
106
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NDSS
2008
IEEE
15 years 6 months ago
2008
IEEE
Fuzz testing is an effective technique for finding security vulnerabilities in software. Traditionally, fuzz testing tools apply random mutations to well-formed inputs of a progr...