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EURODAC
1995
IEEE
127views VHDL» more  EURODAC 1995»
15 years 5 months ago
Layout synthesis for datapath designs
DPLAYOUT is a layout synthesis tool for bit-sliced datapath designs targeting standard-cell libraries. We developed fast and efficient heuristics for placing the cells in a bit-s...
Naveen Buddi, Malgorzata Chrzanowska-Jeske, Charle...
AIIDE
2008
15 years 4 months ago
Automatically Generating Summary Visualizations from Game Logs
In this paper we describe a system called ViGLS (Visualization of Game Log Summaries) that generates summaries of gameplay sessions from game logs. ViGLS automatically produces vi...
Yun-Gyung Cheong, Arnav Jhala, Byung-Chull Bae, R....
WSC
2007
15 years 4 months ago
Reusable tool for 300mm intrabay AMHS modeling and simulation
The transition to 300mm wafer size introduced a lot of new technologies to wafer fabrication facilities that mandated the presence of intrabay automated material handling systems ...
Ahmed El-Nashar, Khaled S. El-Kilany
FDL
2008
IEEE
15 years 3 months ago
RTL Generation of Channel Architecture Templates for a Template-based SoC Design Flow
In this paper, we propose the design methodology for communication channel templates from formal specification to RTL description. In this flow, design and verification start from...
Jinhyun Cho, Soonwoo Choi, Soo Chae
IJCAI
2007
15 years 3 months ago
Analogical Learning in a Turn-Based Strategy Game
A key problem in playing strategy games is learning how to allocate resources effectively. This can be a difficult task for machine learning when the connections between actions a...
Thomas R. Hinrichs, Kenneth D. Forbus