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CAV
2003
Springer
116views Hardware» more  CAV 2003»
15 years 5 months ago
Reasoning with Temporal Logic on Truncated Paths
We consider the problem of reasoning with linear temporal logic on truncated paths. A truncated path is a path that is finite, but not necessarily maximal. Truncated paths arise n...
Cindy Eisner, Dana Fisman, John Havlicek, Yoad Lus...
TARK
2007
Springer
15 years 6 months ago
Full and relative awareness: a decidable logic for reasoning about knowledge of unawareness
In the most popular logics combining knowledge and awareness, it is not possible to express statements about knowledge of unawareness such as “Ann knows that Bill is aware of so...
Thomas Ågotnes, Natasha Alechina
ERSHOV
2001
Springer
15 years 5 months ago
Reexecution-Based Analysis of Logic Programs with Delay Declarations
A general semantics-based framework for the analysis of logic programs with delay declarations is presented. The framework incorporates well known refinement techniques based on r...
Agostino Cortesi, Baudouin Le Charlier, Sabina Ros...
73
Voted
PATMOS
2005
Springer
15 years 6 months ago
A New Model for Timing Jitter Caused by Device Noise in Current-Mode Logic Frequency Dividers
A new method for predicting timing jitter caused by device noise in current-mode logic (CML) frequency dividers is presented. Device noise transformation into jitter is modeled as ...
Marko Aleksic, Nikola Nedovic, K. Wayne Current, V...
132
Voted
EON
2008
15 years 2 months ago
Abductive Synthesis of the Mediator Scenario with jABC and GEM
We reuse here the framework, the setting, and the semantic modelling for the automated synthesis of the SWS Challenge Mediator presented in the companion paper [5], and show how to...
Christian Kubczak, Tiziana Margaria, Matthias Kais...