799 search results - page 76 / 160 » A Logic for Abstract State Machines |
DFT
1998
IEEE
15 years 2 months ago
1998
IEEE
This paper presents a system to evaluate the testability of an on-line testable circuit. The system operates at the RT-level, before the logic synthesis step, and allows for an ex...
103
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LICS
1994
IEEE
15 years 1 months ago
1994
IEEE
We develop a model for timed, reactive computation by extending the asynchronous, untimed concurrent constraint programming model in a simple and uniform way. In the spirit of pro...
IFIP
1993
Springer
15 years 1 months ago
1993
Springer
An advanced Self-Timed Reduced Instruction Set Computer (ST-RISC) architecture is described. It is designed hierarchically, and is formally specified functionally at the various ...
DSD
2006
IEEE
14 years 11 months ago
2006
IEEE
The paper deals with synthesis technique for designing circuits with cascade errors detection. The proposed technique is based on partitioning a scheme into a number of cascades f...
SAMOS
2009
Springer
15 years 4 months ago
2009
Springer
Abstract. Memory access latency can limit microcontroller system performance. SDRAM access control policies impact latency through SDRAM device state. It is shown that execution ti...