Timing optimizations during logic synthesis has become a necessary step to achieve timing closure in VLSI designs. This often involves “shortening” all paths found in the circ...
Limited Switch Dynamic Logic (LSDL), a high performance logic circuit, has been modified by introducing a pseudo-nMOS style load. The resultant circuit consumes less power, primar...
Jayakumaran Sivagnaname, Hung C. Ngo, Kevin J. Now...
This paper proposes a modal extension of Separation Logic [8, 11] for reasoning about data-parallel programs that manipulate heap allocated linked data structures. Separation Logi...
We propose a purely logical framework for planning in partially observable environments. Knowledge states are expressed in a suitable fragment of the epistemic logic S5. We show h...
The event calculus is a logic programming formalism for representing events and their effects especially in database applications. This paper presents the use of the event calculus...