1410 search results - page 254 / 282 » A Logic for Virtual Memory |
106
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CP
2006
Springer
15 years 3 months ago
2006
Springer
This paper describes a complete and efficient solution to the stochastic allocation and scheduling for Multi-Processor System-on-Chip (MPSoC). Given a conditional task graph charac...
FPGA
2006
ACM
15 years 3 months ago
2006
ACM
The paper presents several improvements to state-of-theart in FPGA technology mapping exemplified by a recent advanced technology mapper DAOmap [Chen and Cong, ICCAD `04]. Improve...
FPL
2006
Springer
15 years 3 months ago
2006
Springer
In this paper we present the design and implementation of a dynamically reconfigurable system for packet queue scheduling. Two widely accepted queue schedulers have been implement...
140
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EEF
2000
15 years 3 months ago
2000
Both the logic and the stochastic analysis of discrete-state systems are hindered by the combinatorial growth of the state space underlying a high-level model. In this work, we con...
ISLPED
1995
ACM
15 years 3 months ago
1995
ACM
In current processors, the cache controller, which contains the cache directory and other logic such as tag comparators, is active for each instruction fetch and is responsible fo...