1410 search results - page 56 / 282 » A Logic for Virtual Memory |
102
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CSREAESA
2009
15 years 28 days ago
2009
A Built-In Self-Test (BIST) approach is presented for the Internal Configuration Access Port (ICAP) and Frame Error Correcting Code (ECC) logic cores embedded in Xilinx Virtex-4 an...
FCCM
1997
IEEE
15 years 4 months ago
1997
IEEE
We propose an FPGA chip architecture based on a conventional FPGA logic array core, in which I/O pins are clocked at a much higher rate than that of the logic array that they serv...
113
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ASPLOS
2008
ACM
15 years 1 months ago
2008
ACM
Memory errors are a notorious source of security vulnerabilities that can lead to service interruptions, information leakage and unauthorized access. Because such errors are also ...
EUROPAR
1999
Springer
15 years 4 months ago
1999
Springer
Abstract. This paper presents DAOS, a model for exploitation of Andand Or-parallelism in logic programs. DAOS assumes a physically distributed memory environment and a logically sh...
CF
2006
ACM
15 years 5 months ago
2006
ACM
Bytecode hardware-translation improves the performance of a Java Virtual Machine (JVM) with small hardware resource and complexity overhead. Instruction folding is a technique to ...