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» A Logic for Virtual Memory
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FPGA
1998
ACM
153views FPGA» more  FPGA 1998»
15 years 4 months ago
SMAP: Heterogeneous Technology Mapping for Area Reduction in FPGAs with Embedded Memory Arrays
It has become clear that large embedded con gurable memory arrays will be essential in future FPGAs. Embedded arrays provide high-density high-speed implementations of the storage...
Steven J. E. Wilton
ICCAD
2009
IEEE
118views Hardware» more  ICCAD 2009»
14 years 9 months ago
Memory organization and data layout for instruction set extensions with architecturally visible storage
Present application specific embedded systems tend to choose instruction set extensions (ISEs) based on limitations imposed by the available data bandwidth to custom functional un...
Panagiotis Athanasopoulos, Philip Brisk, Yusuf Leb...
ASPDAC
2001
ACM
117views Hardware» more  ASPDAC 2001»
15 years 3 months ago
Low power techniques for address encoding and memory allocation
- This paper presents encoding techniques to optimize the switching activity on a multiplexed DRAM address bus. The DRAM switching activity can be classified either as external (be...
Wei-Chung Cheng, Massoud Pedram
ENTCS
2008
94views more  ENTCS 2008»
14 years 12 months ago
A Formal Model of Memory Peculiarities for the Verification of Low-Level Operating-System Code
This paper presents our solutions to some problems we encountered in an ongoing attempt to verify the micro-hypervisor currently developed within the Robin project. The problems t...
Hendrik Tews, Tjark Weber, Marcus Völp
HPCA
2006
IEEE
16 years 6 days ago
Software-hardware cooperative memory disambiguation
In high-end processors, increasing the number of in-flight instructions can improve performance by overlapping useful processing with long-latency accesses to the main memory. Buf...
Ruke Huang, Alok Garg, Michael C. Huang