We investigate techniques to design 45nm minimum-energy subthreshold CMOS circuits under timing constraints, considering the practical case of an 8-bit multiplier. We first show ...
We study a clock synchronization protocol for the Chess WSN. First, we model the protocol as a network of timed automata and verify various instances using the Uppaal model checker...
Faranak Heidarian, Julien Schmaltz, Frits W. Vaand...
Abstract: Ambient assisted living (AAL) is a newly emerging term describing a research area with focus on services that support people in their daily life with particular focus on ...
We present and implement an infrastructure for automating the negotiation of business contracts. Underlying our system is a declarative language for both (1) fully-specified, exe...
Daniel M. Reeves, Michael P. Wellman, Benjamin N. ...
The partial reconfiguration feature of some of the currentgeneration Field Programmable Gate Arrays (FPGAs) can improve dependability by detecting and correcting errors in onchip ...