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» A Logical Process Calculus
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VLSID
2009
IEEE
130views VLSI» more  VLSID 2009»
16 years 5 months ago
Reversible Logic Synthesis with Output Permutation
Synthesis of reversible logic has become a very important research area. In recent years several algorithms ? heuristic as well as exact ones ? have been introduced in this area. ...
Daniel Große, Gerhard W. Dueck, Robert Wille...
SIGMOD
2006
ACM
156views Database» more  SIGMOD 2006»
16 years 4 months ago
Data delivery in a service-oriented world: the BEA aquaLogic data services platform
"Wow. I fell asleep listening to SOA music, and when I woke up, I couldn't remember where I'd put my data. Now what?" Has this happened to you? With the new pu...
Michael J. Carey
CAV
2009
Springer
182views Hardware» more  CAV 2009»
15 years 11 months ago
Generalizing DPLL to Richer Logics
The DPLL approach to the Boolean satisfiability problem (SAT) is a combination of search for a satisfying assignment and logical deduction, in which each process guides the other....
Kenneth L. McMillan, Andreas Kuehlmann, Mooly Sagi...
DATE
2008
IEEE
121views Hardware» more  DATE 2008»
15 years 11 months ago
A Bridging Fault Model Where Undetectable Faults Imply Logic Redundancy
We define a robust fault model as a model where the existence of an undetectable fault implies the existence of logic redundancy, or more generally, a suboptimality in the synthe...
Irith Pomeranz, Sudhakar M. Reddy
DSD
2008
IEEE
187views Hardware» more  DSD 2008»
15 years 11 months ago
How to Live with Uncertainties: Exploiting the Performance Benefits of Self-Timed Logic In Synchronous Design
Ultra low power digital systems are key for any future wireless sensor nodes but also inside nomadic embedded systems (such as inside the digital front end of software defined rad...
Giacomo Paci, A. Nackaerts, Francky Catthoor, Luca...