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» A Logical Process Calculus
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AIMSA
2008
Springer
15 years 10 months ago
Nested Precedence Networks with Alternatives: Recognition, Tractability, and Models
Integrated modeling of temporal and logical constraints is important for solving real-life planning and scheduling problems. Logical constrains extend the temporal formalism by rea...
Roman Barták, Ondrej Cepek
DATE
2006
IEEE
133views Hardware» more  DATE 2006»
15 years 10 months ago
Analysis and synthesis of quantum circuits by using quantum decision diagrams
Quantum information processing technology is in its pioneering stage and no proficient method for synthesizing quantum circuits has been introduced so far. This paper introduces a...
Afshin Abdollahi, Massoud Pedram
ADC
2006
Springer
142views Database» more  ADC 2006»
15 years 10 months ago
An optimization for query answering on ALC database
Query answering over OWLs and RDFs on the Semantic Web is, in general, a deductive process. To this end, OWL, a family of web ontology languages based on description logic, has be...
Pakornpong Pothipruk, Guido Governatori
FPGA
2005
ACM
158views FPGA» more  FPGA 2005»
15 years 9 months ago
Automated synthesis for asynchronous FPGAs
We present an automatic logic synthesis method targeted for highperformance asynchronous FPGA (AFPGA) architectures. Our method transforms sequential programs as well as high-leve...
Song Peng, David Fang, John Teifel, Rajit Manohar
FPGA
1998
ACM
140views FPGA» more  FPGA 1998»
15 years 8 months ago
More Wires and Fewer LUTs: A Design Methodology for FPGAs
In designing FPGAs, it is important to achieve a good balance between the number of logic blocks, such as Look-Up Tables (LUTs), and wiring resources. It is dicult to nd an optim...
Atsushi Takahara, Toshiaki Miyazaki, Takahiro Muro...