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» A Logical Process Calculus
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124
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ARITH
1999
IEEE
15 years 8 months ago
Arithmetic with Signed Analog Digits
This paper presents mathematical foundtions of the Overlap Resolution Number System (ORNS) which employs signed Continuous Valued Digits (CVD's). ORNS is a redundant Number S...
Aryan Saed, Majid Ahmadi, Graham A. Jullien
129
Voted
DATE
1999
IEEE
123views Hardware» more  DATE 1999»
15 years 8 months ago
Accounting for Various Register Allocation Schemes During Post-Synthesis Verification of RTL Designs
This paper reports a formal methodology for verifying a broad class of synthesized register-transfer-level (RTL) designs by accommodating various register allocation/optimization ...
Nazanin Mansouri, Ranga Vemuri
122
Voted
DATE
1997
IEEE
107views Hardware» more  DATE 1997»
15 years 8 months ago
Acceleration of behavioral simulation on simulation specific machines
Behavioral simulation is faster than gate-level logic simulation, however, the simulation speed is too slow for large systems. Simulation specific machines accelerated simulation ...
Minoru Shoji, Fumiyasu Hirose, Shintaro Shimogori,...
149
Voted
LICS
1994
IEEE
15 years 7 months ago
Foundations of Timed Concurrent Constraint Programming
We develop a model for timed, reactive computation by extending the asynchronous, untimed concurrent constraint programming model in a simple and uniform way. In the spirit of pro...
Vijay A. Saraswat, Radha Jagadeesan, Vineet Gupta
ER
2006
Springer
105views Database» more  ER 2006»
15 years 7 months ago
UN/CEFACT'S Modeling Methodology (UMM): A UML Profile for B2B e-Commerce
Abstract. The United Nation's Centre for Trade Facilitation and Electronic Business (UN/CEFACT) is an e-business standardization body. It is known from its work on UN/EDIFACT ...
Birgit Hofreiter, Christian Huemer, Philipp Liegl,...