Sciweavers

3239 search results - page 517 / 648
» A Logical Process Calculus
Sort
View
113
Voted
ICCD
2004
IEEE
98views Hardware» more  ICCD 2004»
15 years 9 months ago
Thermal-Aware IP Virtualization and Placement for Networks-on-Chip Architecture
Networks-on-Chip (NoC), a new SoC paradigm, has been proposed as a solution to mitigate complex on-chip interconnect problems. NoC architecture consists of a collection of IP core...
Wei-Lun Hung, Charles Addo-Quaye, Theo Theocharide...
82
Voted
ICCAD
2008
IEEE
140views Hardware» more  ICCAD 2008»
15 years 9 months ago
To SAT or not to SAT: Ashenhurst decomposition in a large scale
Functional decomposition is a fundamental operation in logic synthesis. Prior BDD-based approaches to functional decomposition suffer from the memory explosion problem and do not...
Hsuan-Po Lin, Jie-Hong Roland Jiang, Ruei-Rung Lee
ASAP
2008
IEEE
167views Hardware» more  ASAP 2008»
15 years 7 months ago
Extending the SIMPPL SoC architectural framework to support application-specific architectures on multi-FPGA platforms
Process technology has reduced in size such that it is possible to implement complete applicationspecific architectures as Systems-on-Chip (SoCs) using both Application-Specific I...
David Dickin, Lesley Shannon
90
Voted
ICASSP
2008
IEEE
15 years 7 months ago
Accurate models for estimating area and power of FPGA implementations
This paper presents accurate area and power estimation models for implementations using FPGAs from the Xilinx Virtex-2Pro family. These models are designed to facilitate efficien...
Lanping Deng, Kanwaldeep Sobti, Chaitali Chakrabar...
114
Voted
DASFAA
2007
IEEE
266views Database» more  DASFAA 2007»
15 years 7 months ago
Compatibility Analysis and Mediation-Aided Composition for BPEL Services
In Service Oriented Architecture (SOA), the need for inter-service compatibility analysis has gone beyond what existing service composition/ verification approaches can handle. Giv...
Wei Tan, Fangyan Rao, Yushun Fan, Jun Zhu