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» A Low Power 2-D DCT Chip Design Using Direct 2-D Algorithm
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ASPDAC
1998
ACM
96views Hardware» more  ASPDAC 1998»
15 years 8 months ago
A Low Power 2-D DCT Chip Design Using Direct 2-D Algorithm
Liang-Gee Chen, Juing-Ying Jiu, Hao-Chieh Chang, Y...
155
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ITC
2003
IEEE
168views Hardware» more  ITC 2003»
15 years 9 months ago
A Built-In Self-Repair Scheme for Semiconductor Memories with 2-D Redundancy
Embedded memories are among the most widely used cores in current system-on-chip (SOC) implementations. Memory cores usually occupy a significant portion of the chip area, and do...
Jin-Fu Li, Jen-Chieh Yeh, Rei-Fu Huang, Cheng-Wen ...
DAC
1995
ACM
15 years 7 months ago
Orthogonal Greedy Coupling - A New Optimization Approach to 2-D FPGA Routing
We propose a novel optimization scheme that can improve the routing by reducing a newly observed router decaying effect. A pair of greedy-grow algorithms, each emphasizing a diffe...
Yu-Liang Wu, Malgorzata Marek-Sadowska
146
Voted
BMCBI
2010
218views more  BMCBI 2010»
15 years 3 months ago
Fast multi-core based multimodal registration of 2D cross-sections and 3D datasets
Background: Solving bioinformatics tasks often requires extensive computational power. Recent trends in processor architecture combine multiple cores into a single chip to improve...
Michael Scharfe, Rainer Pielot, Falk Schreiber
127
Voted
DATE
2007
IEEE
156views Hardware» more  DATE 2007»
15 years 10 months ago
Process variation tolerant low power DCT architecture
: 2-D Discrete Cosine Transform (DCT) is widely used as the core of digital image and video compression. In this paper, we present a novel DCT architecture that allows aggressive v...
Nilanjan Banerjee, Georgios Karakonstantis, Kaushi...