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» A Low Power Highly Associative Cache for Embedded Systems
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ISVLSI
2008
IEEE
158views VLSI» more  ISVLSI 2008»
15 years 4 months ago
Improving Energy Efficiency of Configurable Caches via Temperature-Aware Configuration Selection
Active power used to be the primary contributor to total power dissipation of CMOS designs, but with the technology scaling, the share of leakage in total power consumption of dig...
Hamid Noori, Maziar Goudarzi, Koji Inoue, Kazuaki ...
76
Voted
SIGMETRICS
1991
ACM
15 years 1 months ago
Implementing Stack Simulation for Highly-Associative Memories
Prior to this work, all implementations of stack simulation [MGS70] required more than linear time to process an address trace. In particular these implementations are often slow ...
Yul H. Kim, Mark D. Hill, David A. Wood
DATE
2000
IEEE
90views Hardware» more  DATE 2000»
15 years 2 months ago
Fast Cache and Bus Power Estimation for Parameterized System-on-a-Chip Design
We present a technique for fast estimation of the power consumed by the cache and bus sub-system of a parameterized system-on-a-chip design for a given application. The technique ...
Jörg Henkel, Tony Givargis, Frank Vahid
JSA
2006
167views more  JSA 2006»
14 years 9 months ago
Pattern-driven prefetching for multimedia applications on embedded processors
Multimedia applications in general and video processing, such as the MPEG4 Visual stream decoders, in particular are increasingly popular and important workloads for future embedd...
Hassan Sbeyti, Smaïl Niar, Lieven Eeckhout
87
Voted
HPCA
2005
IEEE
15 years 10 months ago
Tapping ZettaRAMTM for Low-Power Memory Systems
ZettaRAMTM is a new memory technology under development by ZettaCoreTM as a potential replacement for conventional DRAM. The key innovation is replacing the conventional capacitor...
Ravi K. Venkatesan, Ahmed S. Al-Zawawi, Eric Roten...