154 search results - page 11 / 31 » A Low Power Highly Associative Cache for Embedded Systems |
88
Voted
DAC
2008
ACM
15 years 10 months ago
2008
ACM
Today, embedded processors are expected to be able to run complex, algorithm-heavy applications that were originally designed and coded for general-purpose processors. As a result...
NOCS
2007
IEEE
15 years 3 months ago
2007
IEEE
The paper introduces Network-on-Chip (NoC) design methodology and low cost mechanisms for supporting efficient cache access and cache coherency in future high-performance Chip Mul...
GLVLSI
2010
IEEE
15 years 2 months ago
2010
IEEE
On-chip memory organization is one of the most important aspects that can influence the overall system behavior in multiprocessor systems. Following the trend set by high-perform...
DATE
2008
IEEE
15 years 4 months ago
2008
IEEE
—The contribution of memory latency to execution time continues to increase, and latency hiding mechanisms become ever more important for efficient processor design. While high-...
EUC
2005
Springer
15 years 3 months ago
2005
Springer
Abstract. Most of the new embedded systems require high performance processors at low power. To cater to these needs, most semiconductor companies are designing multi-core processo...