154 search results - page 5 / 31 » A Low Power Highly Associative Cache for Embedded Systems |
91
Voted
IPPS
1998
IEEE
15 years 1 months ago
1998
IEEE
In this paper, we present several novel strategies to improve software controlled cache utilization, so as to achieve lower power requirements for multi-media and signal processin...
89
Voted
DATE
1999
IEEE
15 years 1 months ago
1999
IEEE
This paper proposes a methodology to evaluate the effects of encodings on the power consumption of system-level buses in the presence of multi-level cache memories. The proposed m...
CASES
2006
ACM
15 years 3 months ago
2006
ACM
We propose an architecture that uses NAND flash memory to reduce main memory power in web server platforms. Our architecture uses a two level file buffer cache composed of a re...
VLSID
2009
IEEE
15 years 10 months ago
2009
IEEE
Abstract-- Single-ended static random access memory (SESRAM) is well known for their tremendous potential of low active power and leakage dissipations. In this paper, we present a ...
DATE
2003
IEEE
15 years 2 months ago
2003
IEEE
This paper presents a on-chip stack based memory organization that effectively reduces the energy dissipation in programmable embedded system architectures. Most embedded systems ...