154 search results - page 6 / 31 » A Low Power Highly Associative Cache for Embedded Systems |
115
Voted
GLVLSI
2005
IEEE
15 years 6 months ago
2005
IEEE
The instruction cache is a popular target for optimizations of microprocessor-based systems because of the cache’s high impact on system performance and power, and because of th...
121
Voted
HIPEAC
2007
Springer
15 years 6 months ago
2007
Springer
Abstract. In this paper, we propose a novel approach to reduce dynamic power in set-associative caches that leverages on a leakage-saving proposal, namely Cache Decay. We thus open...
92
Voted
ICCAD
2002
IEEE
15 years 9 months ago
2002
IEEE
Embedded system programs tend to spend much time in small loops. Introducing a very small loop cache into the instruction memory hierarchy has thus been shown to substantially red...
120
Voted
ISSS
2002
IEEE
15 years 5 months ago
2002
IEEE
Adding a small loop cache to a microprocessor has been shown to reduce average instruction fetch energy for various sets of embedded system applications. With the advent of core-b...
116
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ICPP
2002
IEEE
15 years 5 months ago
2002
IEEE
A software cache implements instruction and data caching entirely in software. Dynamic binary rewriting offers a means to specialize the software cache miss checks at cache miss t...