Sciweavers

350 search results - page 15 / 70
» A Low Power TLB Structure for Embedded Systems
Sort
View
ISCAS
2011
IEEE
342views Hardware» more  ISCAS 2011»
14 years 1 months ago
Parallel Dynamic Voltage and Frequency Scaling for stream decoding using a multicore embedded system
—Parallel structures may be used to increase a system processing speed in case of large amount of data or highly complex calculations. Dynamic Voltage and Frequency Scaling (DVFS...
Ying-Xun Lai, Yueh-Min Huang, Chin-Feng Lai, Ljilj...
ASPDAC
2006
ACM
116views Hardware» more  ASPDAC 2006»
15 years 3 months ago
Abridged addressing: a low power memory addressing strategy
Abstract— The memory subsystem is known to comprise a significant fraction of the power dissipation in embedded systems. The memory addressing strategy, which determines the seq...
Preeti Ranjan Panda
EVOW
2011
Springer
14 years 1 months ago
Two Iterative Metaheuristic Approaches to Dynamic Memory Allocation for Embedded Systems
Abstract. Electronic embedded systems designers aim at finding a tradeoff between cost and power consumption. As cache memory management has been shown to have a significant imp...
María Soto, André Rossi, Marc Sevaux
JCSC
2002
87views more  JCSC 2002»
14 years 9 months ago
Power Estimator Development for Embedded System Memory Tuning
Memory accesses account for a large percentage of total power in microprocessor-based embedded systems. The increasing use of microprocessor cores and synthesis, rather than prefa...
Frank Vahid, Tony Givargis, Susan Cotterell
DAC
2001
ACM
15 years 10 months ago
Power-Aware Scheduling under Timing Constraints for Mission-Critical Embedded Systems
Power-aware systems are those that must make the best use of available power. They subsume traditional low-power systems in that they must not only minimize power when the budget ...
Jinfeng Liu, Pai H. Chou, Nader Bagherzadeh, Fadi ...