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» A Low Power TLB Structure for Embedded Systems
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JCP
2008
160views more  JCP 2008»
14 years 9 months ago
A Bluetooth-based Sensor Node for Low-Power Ad Hoc Networks
TCP/IP has recently taken promising steps toward being a viable communication architecture for networked sensor nodes. Furthermore, the use of Bluetooth can enable a wide range of ...
Jens Eliasson, Per Lindgren, Jerker Delsing
ITC
2003
IEEE
170views Hardware» more  ITC 2003»
15 years 3 months ago
Double-Tree Scan: A Novel Low-Power Scan-Path Architecture
In a scan-based system with a large number of flip-flops, a major component of power is consumed during scanshift and clocking operation in test mode. In this paper, a novel scan-...
Bhargab B. Bhattacharya, Sharad C. Seth, Sheng Zha...
ETS
2007
IEEE
128views Hardware» more  ETS 2007»
14 years 11 months ago
Selecting Power-Optimal SBST Routines for On-Line Processor Testing
Software-Based Self-Test (SBST) has emerged as an effective strategy for on-line testing of processors integrated in non-safety critical embedded system applications. Among the mo...
Andreas Merentitis, Nektarios Kranitis, Antonis M....
ICCAD
2003
IEEE
111views Hardware» more  ICCAD 2003»
15 years 6 months ago
Formal Methods for Dynamic Power Management
Dynamic Power Management or DPM refers to the problem of judicious application of various low power techniques based on runtime conditions in an embedded system to minimize the to...
Rajesh K. Gupta, Sandy Irani, Sandeep K. Shukla
ISLPED
1999
ACM
129views Hardware» more  ISLPED 1999»
15 years 2 months ago
Power scalable processing using distributed arithmetic
A recent trend in low power design has been the employment of reduced precision processing methods for decreasing arithmetic activity and average power dissipation. Such designs c...
Rajeevan Amirtharajah, Thucydides Xanthopoulos, An...