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» A Low Power TLB Structure for Embedded Systems
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ICDE
2005
IEEE
107views Database» more  ICDE 2005»
15 years 11 months ago
Spatiotemporal Annotation Graph (STAG): A Data Model for Composite Digital Objects
In this demonstration, we present a database over complex documents, which, in addition to a structured text content, also has update information, annotations, and embedded object...
Smriti Yamini, Amarnath Gupta
DSD
2008
IEEE
187views Hardware» more  DSD 2008»
15 years 4 months ago
How to Live with Uncertainties: Exploiting the Performance Benefits of Self-Timed Logic In Synchronous Design
Ultra low power digital systems are key for any future wireless sensor nodes but also inside nomadic embedded systems (such as inside the digital front end of software defined rad...
Giacomo Paci, A. Nackaerts, Francky Catthoor, Luca...
DAC
2008
ACM
15 years 10 months ago
Miss reduction in embedded processors through dynamic, power-friendly cache design
Today, embedded processors are expected to be able to run complex, algorithm-heavy applications that were originally designed and coded for general-purpose processors. As a result...
Garo Bournoutian, Alex Orailoglu
ACNS
2004
Springer
247views Cryptology» more  ACNS 2004»
15 years 3 months ago
Low-Latency Cryptographic Protection for SCADA Communications
Abstract. Supervisory Control And Data Acquisition (SCADA) systems are real-time process control systems that are widely deployed throughout critical infrastructure sectors includi...
Andrew K. Wright, John A. Kinast, Joe McCarty
GLVLSI
2009
IEEE
158views VLSI» more  GLVLSI 2009»
15 years 1 months ago
Exploration of memory hierarchy configurations for efficient garbage collection on high-performance embedded systems
Modern embedded devices (e.g., PDAs, mobile phones) are now incorporating Java as a very popular implementation language in their designs. These new embedded systems include multi...
José Manuel Velasco, David Atienza, Katzali...