Sciweavers

350 search results - page 37 / 70
» A Low Power TLB Structure for Embedded Systems
Sort
View
GLVLSI
2005
IEEE
124views VLSI» more  GLVLSI 2005»
15 years 3 months ago
A first look at the interplay of code reordering and configurable caches
The instruction cache is a popular target for optimizations of microprocessor-based systems because of the cache’s high impact on system performance and power, and because of th...
Ann Gordon-Ross, Frank Vahid, Nikil Dutt
CHI
2005
ACM
15 years 10 months ago
A logic block enabling logic configuration by non-experts in sensor networks
Recent years have seen the evolution of networks of tiny low power computing blocks, known as sensor networks. In one class of sensor networks, a non-expert user, who has little o...
Susan Cotterell, Frank Vahid
GLVLSI
2010
IEEE
187views VLSI» more  GLVLSI 2010»
15 years 2 months ago
Write activity reduction on flash main memory via smart victim cache
Flash Memory is a desirable candidate for main memory replacement in embedded systems due to its low leakage power consumption, higher density and non-volatility characteristics. ...
Liang Shi, Chun Jason Xue, Jingtong Hu, Wei-Che Ts...
CSE
2009
IEEE
15 years 1 months ago
Rotation Scheduling and Voltage Assignment to Minimize Energy for SoC
— Low energy consumption is a critical issue in embedded systems design. As the technology feature sizes of SoC (Systems on Chip) become smaller and smaller, the percentage of le...
Meikang Qiu, Laurence Tianruo Yang, Edwin Hsing-Me...
VLSID
2008
IEEE
138views VLSI» more  VLSID 2008»
15 years 10 months ago
Memory Architecture Exploration Framework for Cache Based Embedded SOC
Today's feature-rich multimedia products require embedded system solution with complex System-on-Chip (SoC) to meet market expectations of high performance at a low cost and l...
T. S. Rajesh Kumar, C. P. Ravikumar, R. Govindaraj...