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» A Low Power TLB Structure for Embedded Systems
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CODES
2005
IEEE
14 years 11 months ago
An efficient direct mapped instruction cache for application-specific embedded systems
Caches may consume half of a microprocessor’s total power and cache misses incur accessing off-chip memory, which is both time consuming and energy costly. Therefore, minimizing...
Chuanjun Zhang
CSREAESA
2007
14 years 11 months ago
The Effect of Nanometer-Scale Technologies on the Cache Size Selection for Low Energy Embedded Systems
- Several studies have shown that cache memories account for more than 40% of the total energy consumed in processor-based embedded systems. In microscale technology nodes, active ...
Hamid Noori, Maziar Goudarzi, Koji Inoue, Kazuaki ...
VLSID
2009
IEEE
119views VLSI» more  VLSID 2009»
15 years 10 months ago
Single Ended Static Random Access Memory for Low-Vdd, High-Speed Embedded Systems
Abstract-- Single-ended static random access memory (SESRAM) is well known for their tremendous potential of low active power and leakage dissipations. In this paper, we present a ...
Jawar Singh, Jimson Mathew, Saraju P. Mohanty, Dhi...
MOBIHOC
2000
ACM
15 years 2 months ago
Low power rendezvous in embedded wireless networks
ln the future, wireless networking will be embedded into a wide variety of common, everyday objects [1]. In many embedded networking situations, the communicating nodes will be ver...
Terry Todd, Frazer Bennett, Alan Jones
DATE
2007
IEEE
99views Hardware» more  DATE 2007»
15 years 4 months ago
Very wide register: an asymmetric register file organization for low power embedded processors
In current embedded systems processors, multi-ported register files are one of the most power hungry parts of the processor, even when they are clustered. This paper presents a n...
Praveen Raghavan, Andy Lambrechts, Murali Jayapala...