Sciweavers

743 search results - page 21 / 149
» A Mechanism for Communicating in Dynamically Reconfigurable ...
Sort
View
VLSISP
2008
123views more  VLSISP 2008»
14 years 11 months ago
Implementation of a Coarse-Grained Reconfigurable Media Processor for AVC Decoder
ADRES (Architecture for Dynamically Reconfigurable Embedded Systems) is a templatized coarse-grained reconfigurable processor architecture. It targets at embedded applications whic...
Bingfeng Mei, Bjorn De Sutter, Tom Vander Aa, M. W...
CODES
1997
IEEE
15 years 4 months ago
Optimizing communication in embedded system co-simulation
The Pia hardware-software co-simulator provides substantial speedups over traditional co-simulation methods by permitting dynamic changes in the level of detail when simulating co...
Ken Hines, Gaetano Borriello
ICDCSW
2009
IEEE
15 years 6 months ago
Embedded Virtual Machines for Robust Wireless Control Systems
Embedded wireless networks have largely focused on openloop sensing and monitoring. To address actuation in closedloop wireless control systems there is a strong need to re-think ...
Rahul Mangharam, Miroslav Pajic
PERCOM
2007
ACM
15 years 11 months ago
The RUNES Middleware for Networked Embedded Systems and its Application in a Disaster Management Scenario
Due to the inherent nature of their heterogeneity, resource scarcity and dynamism, the provision of middleware for future networked embedded environments is a challenging task. In...
Paolo Costa, Geoff Coulson, Richard Gold, Manish L...
FPL
2005
Springer
96views Hardware» more  FPL 2005»
15 years 5 months ago
Dynamic Reconfiguration with hardwired Networks-on-Chip on future FPGAs
Due to their layered approach, Networks-on-Chip (NoC) are a promising communication backbone in the field of heterogeneous dynamically reconfigurable systems. In this paper a fu...
Ronald Hecht, Stephan Kubisch, Andreas Herrholtz, ...