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DAC
2002
ACM
16 years 2 months ago
Dynamic hardware plugins in an FPGA with partial run-time reconfiguration
Tools and a design methodology have been developed to support partial run-time reconfiguration of FPGA logic on the Field Programmable Port Extender. High-speed Internet packet pr...
Edson L. Horta, John W. Lockwood, David E. Taylor,...
FCCM
2004
IEEE
103views VLSI» more  FCCM 2004»
15 years 5 months ago
A Dynamically-Reconfigurable, Power-Efficient Turbo Decoder
The development of turbo codes has allowed for nearShannon limit information transfer in modern communication systems. Although turbo decoding is viewed as superior to alternate d...
Jian Liang, Russell Tessier, Dennis Goeckel
SAMOS
2010
Springer
14 years 12 months ago
Identifying communication models in Process Networks derived from Weakly Dynamic Programs
—Process Networks (PNs) is an appealing computation ion helping to specify an application in parallel form and realize it on parallel platforms. The key questions to be answered ...
Dmitry Nadezhkin, Todor Stefanov
GECCO
2009
Springer
193views Optimization» more  GECCO 2009»
15 years 6 months ago
Optimization of dynamic memory managers for embedded systems using grammatical evolution
New portable consumer embedded devices must execute multimedia applications (e.g., 3D games, video players and signal processing software, etc.) that demand extensive memory acces...
José L. Risco-Martín, David Atienza,...
GECCO
2010
Springer
170views Optimization» more  GECCO 2010»
15 years 6 months ago
Improving reliability of embedded systems through dynamic memory manager optimization using grammatical evolution
Technology scaling has offered advantages to embedded systems, such as increased performance, more available memory and reduced energy consumption. However, scaling also brings a...
José Manuel Colmenar, José L. Risco-...