109 search results - page 12 / 22 » A Methodology for Large-Scale Hardware Verification |
ICCAD
2003
IEEE
15 years 6 months ago
2003
IEEE
— In this paper we consider the problem of finding a smaller RLCM circuit that approximately replicates the behavior (up to a certain frequency) of a given RLCM circuit. Targeted...
ICCAD
1999
IEEE
15 years 1 months ago
1999
IEEE
We introduce a new method of verifying the timing of custom CMOS circuits. Due to the exponential number of patterns required, traditional simulation methods are unable to exhaust...
ECBS
2006
IEEE
15 years 1 months ago
2006
IEEE
We present in this paper a unified paradigm for the verification and validation of software and systems engineering design models expressed in UML 2.0 or SysML. This paradigm reli...
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ECBS
2007
IEEE
15 years 1 months ago
2007
IEEE
We present in this paper a new approach for the automatic verification and performance analysis of SysML activity diagrams. Since timeliness is important in the design and analysi...
CSCWD
2009
Springer
15 years 4 months ago
2009
Springer
Constrained random simulation methodology still plays an important role in hardware verification due to the limited scalability of formal verification, especially for the large an...