109 search results - page 15 / 22 » A Methodology for Large-Scale Hardware Verification |
88
Voted
CAV
2007
Springer
15 years 1 months ago
2007
Springer
Abstract. A recent approach to automated assume-guarantee reasoning (AGR) for concurrent systems relies on computing environment assumptions for components using the L algorithm fo...
ICCAD
2006
IEEE
15 years 6 months ago
2006
IEEE
The use of CMOS nanometer technologies at 65 nm and below will pose serious challenges on the design of mixed-signal integrated systems in the very near future. Rising design comp...
ICCAD
2002
IEEE
15 years 6 months ago
2002
IEEE
The challenges for developing an ESD (Electro-static Discharge) layout extractor originate from unconventional layout patterns of ESD protection devices, parasitic ESD device extr...
DDECS
2007
IEEE
15 years 4 months ago
2007
IEEE
: As scan compression replaces the traditional scan it is important to understand how it works with power. DFT MAX represents one of the two primary scan compression solutions used...
ASYNC
2002
IEEE
15 years 2 months ago
2002
IEEE
Wire and gate delays are accounted to have equal, or nearly equal, effect on circuit behavior in modern design techniques. This paper introduces a new approach to verify circuits ...