109 search results - page 8 / 22 » A Methodology for Large-Scale Hardware Verification |
DATE
1999
IEEE
1999
IEEE
Accounting for Various Register Allocation Schemes During Post-Synthesis Verification of RTL Designs
15 years 1 months ago
This paper reports a formal methodology for verifying a broad class of synthesized register-transfer-level (RTL) designs by accommodating various register allocation/optimization ...
CAV
2001
Springer
15 years 1 months ago
2001
Springer
Compositional model checking is used to verify a processor microarchitecture containing most of the features of a modern microprocessor, including branch prediction, speculative ex...
FPGA
2003
ACM
15 years 2 months ago
2003
ACM
This paper describes the hardware implementation of a real-time, large-scale, multi-chip FPGA (Field Programmable Gate Array) based emulation engine with a capacity of 10 million ...
DATE
2004
IEEE
15 years 1 months ago
2004
IEEE
Productivity data for IC designs indicates an exponential increase in design time and cost with the number of elements that are to be included in a device. Present applications re...
ISQED
2005
IEEE
15 years 3 months ago
2005
IEEE
Today's System-on-a-Chip (SoC) design methodology provides an efficient way to develop highly integrated systems on a single chip by utilizing pre-designed intellectual prope...