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ISCA
1993
IEEE
137views Hardware» more  ISCA 1993»
15 years 7 months ago
Transactional Memory: Architectural Support for Lock-Free Data Structures
A shared data structure is lock-free if its operations do not require mutual exclusion. If one process is interrupted in the middle of an operation, other processes will not be pr...
Maurice Herlihy, J. Eliot B. Moss
120
Voted
ISCA
1993
IEEE
137views Hardware» more  ISCA 1993»
15 years 7 months ago
Architectural Support for Translation Table Management in Large Address Space Machines
Virtual memoy page translation tables provide mappings from virtual to physical addresses. When the hardware controlled Tratmlation L.ookaside Buffers (TLBs) do not contain a tran...
Jerome C. Huck, Jim Hays
125
Voted
IPPS
1994
IEEE
15 years 7 months ago
Parallel Evaluation of a Parallel Architecture by Means of Calibrated Emulation
A parallel transputer-based emulator has been developed to evaluate the DDM--ahighlyparallel virtual shared memory architecture. The emulator provides performance results of a har...
Henk L. Muller, Paul W. A. Stallard, David H. D. W...
156
Voted
ISCAS
1994
IEEE
138views Hardware» more  ISCAS 1994»
15 years 7 months ago
High-Throughput Data Compressor Designs Using Content Addressable Memory
This paper presents a novel VLSI architecture for high-speed data compressor designs which implement the well-known LZ77 algorithm. The architecture mainly consists of three units...
Ren-Yang Yang, Chen-Yi Lee
143
Voted
ASPLOS
1992
ACM
15 years 7 months ago
Design and Evaluation of a Compiler Algorithm for Prefetching
Software-controlled data prefetching is a promising technique for improving the performance of the memory subsystem to match today's high-performance processors. While prefet...
Todd C. Mowry, Monica S. Lam, Anoop Gupta
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