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» A Modal Model of Memory
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102
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MTDT
2000
IEEE
137views Hardware» more  MTDT 2000»
15 years 5 months ago
Diagnostic Testing of Embedded Memories Based on Output Tracing
A new approach to diagnostic testing of embedded memories is presented which enables the design of tests that provide complete detection and distinguishing of all faults in a give...
Dirk Niggemeyer, Elizabeth M. Rudnick, Michael Red...
118
Voted
CORR
2006
Springer
112views Education» more  CORR 2006»
15 years 20 days ago
High-level synthesis under I/O Timing and Memory constraints
The design of complex Systems-on-Chips implies to take into account communication and memory access constraints for the integration of dedicated hardware accelerator. In this paper...
Philippe Coussy, Gwenolé Corre, Pierre Bome...
108
Voted
ICASSP
2008
IEEE
15 years 7 months ago
Address assignment sensitive variable partitioning and scheduling for DSPS with multiple memory banks
Multiple memory banks design is employed in many high performance DSP processors. This architectural feature supports higher memory bandwidth by allowing multiple data memory acce...
Chun Jason Xue, Tiantian Liu, Zili Shao, Jingtong ...
87
Voted
ICCAD
1997
IEEE
144views Hardware» more  ICCAD 1997»
15 years 4 months ago
Exploiting off-chip memory access modes in high-level synthesis
Memory-intensive behaviors often contain large arrays that are synthesized into off-chip memories. With the increasing gap between on-chip and off-chip memory access delays, it is...
Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nico...
IROS
2006
IEEE
104views Robotics» more  IROS 2006»
15 years 6 months ago
Stiffness Modeling of a Spatial 3-DOF Compliant Parallel Micromanipulator
— The stiffness modeling for a compliant parallel manipulator (CPM) is very important since it provides a basis for the characterization of static, modal, and dynamic behavior of...
Qingsong Xu, Yangmin Li