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MICRO
2008
IEEE
109views Hardware» more  MICRO 2008»
15 years 10 months ago
Dependence-aware transactional memory for increased concurrency
—Transactional memory (TM) is a promising paradigm for helping programmers take advantage of emerging multicore platforms. Though they perform well under low contention, hardware...
Hany E. Ramadan, Christopher J. Rossbach, Emmett W...
ESTIMEDIA
2007
Springer
15 years 10 months ago
Network Calculus Applied to Verification of Memory Access Performance in SoCs
SoCs for multimedia applications typically use only one port to off-chip DRAM for cost reasons. The sharing of interconnect and the off-chip DRAM port by several IP blocks makes t...
Tomas Henriksson, Pieter van der Wolf, Axel Jantsc...
114
Voted
IWINAC
2005
Springer
15 years 9 months ago
Spatial navigation based on novelty mediated autobiographical memory
This paper presents a method for spatial navigation performed mainly on past experiences. The past experiences are remembered in their temporal context, i.e. as episodes of events....
Emilia I. Barakova, Tino Lourens
PPOPP
2003
ACM
15 years 9 months ago
User-controllable coherence for high performance shared memory multiprocessors
In programming high performance applications, shared address-space platforms are preferable for fine-grained computation, while distributed address-space platforms are more suita...
Collin McCurdy, Charles N. Fischer
PDP
2002
IEEE
15 years 9 months ago
A Parametrized Algorithm that Implements Sequential, Causal, and Cache Memory Consistency
In this paper we present an algorithm that can be used to implement sequential, causal, or cache consistency in distributed shared memory (DSM) systems. For this purpose it has a ...
Ernesto Jiménez, Antonio Fernández, ...