Sciweavers

3394 search results - page 561 / 679
» A Modal Model of Memory
Sort
View
ICCD
2001
IEEE
98views Hardware» more  ICCD 2001»
16 years 1 months ago
In-Line Interrupt Handling for Software-Managed TLBs
The general-purpose precise interrupt mechanism, which has long been used to handle exceptional conditions that occur infrequently, is now being used increasingly often to handle ...
Aamer Jaleel, Bruce L. Jacob
ICCAD
2008
IEEE
246views Hardware» more  ICCAD 2008»
16 years 1 months ago
MC-Sim: an efficient simulation tool for MPSoC designs
The ability to integrate diverse components such as processor cores, memories, custom hardware blocks and complex network-on-chip (NoC) communication frameworks onto a single chip...
Jason Cong, Karthik Gururaj, Guoling Han, Adam Kap...
ISPASS
2010
IEEE
15 years 11 months ago
Synthesizing memory-level parallelism aware miniature clones for SPEC CPU2006 and ImplantBench workloads
Abstract—We generate and provide miniature synthetic benchmark clones for modern workloads to solve two pre-silicon design challenges, namely: 1) huge simulation time (weeks to m...
Karthik Ganesan, Jungho Jo, Lizy K. John
CGO
2009
IEEE
15 years 11 months ago
Stream Compilation for Real-Time Embedded Multicore Systems
Abstract—Multicore systems have not only become ubiquitous in the desktop and server worlds, but are also becoming the standard in the embedded space. Multicore offers programabi...
Yoonseo Choi, Yuan Lin, Nathan Chong, Scott A. Mah...
LCTRTS
2009
Springer
15 years 11 months ago
Eliminating the call stack to save RAM
Most programming languages support a call stack in the programming model and also in the runtime system. We show that for applications targeting low-power embedded microcontroller...
Xuejun Yang, Nathan Cooprider, John Regehr