3394 search results - page 572 / 679 » A Modal Model of Memory |
117
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VLSID
2004
IEEE
16 years 4 months ago
2004
IEEE
The detection of all open defects within 6T SRAM cells is always a challenge due to the significant test time requirements. This paper proposes a new design-for-test (DFT) techniq...
144
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VLSID
2003
IEEE
16 years 4 months ago
2003
IEEE
Most verification tools and methodologies such as model checking, equivalence checking, hardware verification, software verification, and hardware-software coverification often fl...
132
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HPCA
2007
IEEE
16 years 4 months ago
2007
IEEE
With the advent of ubiquitous multi-core architectures, a major challenge is to simplify parallel programming. One way to tame one of the main sources of programming complexity, n...
127
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HPCA
2006
IEEE
16 years 4 months ago
2006
IEEE
Transactional memory (TM) provides an easy-to-use and high-performance parallel programming model for the upcoming chip-multiprocessor systems. Several researchers have proposed a...
250
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POPL
2007
ACM
16 years 4 months ago
2007
ACM
Reuse distance (i.e. LRU stack distance) precisely characterizes program locality and has been a basic tool for memory system research since the 1970s. However, the high cost of m...