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» A Modal Model of Memory
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106
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ALGOSENSORS
2007
Springer
15 years 6 months ago
Maximal Breach in Wireless Sensor Networks: Geometric Characterization and Algorithms
e for abstract modeling, algorithmic design and analysis to achieve provably efficient, scalable and fault-tolerant realizations of such huge, highly-dynamic, complex, non-conventi...
Anirvan DuttaGupta, Arijit Bishnu, Indranil Sengup...
FPGA
2007
ACM
124views FPGA» more  FPGA 2007»
15 years 6 months ago
A practical FPGA-based framework for novel CMP research
Chip-multiprocessors are quickly gaining momentum in all segments of computing. However, the practical success of CMPs strongly depends on addressing the difficulty of multithread...
Sewook Wee, Jared Casper, Njuguna Njoroge, Yuriy T...
IEEEPACT
2006
IEEE
15 years 6 months ago
Communist, utilitarian, and capitalist cache policies on CMPs: caches as a shared resource
As chip multiprocessors (CMPs) become increasingly mainstream, architects have likewise become more interested in how best to share a cache hierarchy among multiple simultaneous t...
Lisa R. Hsu, Steven K. Reinhardt, Ravishankar R. I...
88
Voted
MICRO
2006
IEEE
84views Hardware» more  MICRO 2006»
15 years 6 months ago
Reunion: Complexity-Effective Multicore Redundancy
To protect processor logic from soft errors, multicore redundant architectures execute two copies of a program on separate cores of a chip multiprocessor (CMP). Maintaining identi...
Jared C. Smolens, Brian T. Gold, Babak Falsafi, Ja...
117
Voted
VALUETOOLS
2006
ACM
167views Hardware» more  VALUETOOLS 2006»
15 years 6 months ago
Detailed cache simulation for detecting bottleneck, miss reason and optimization potentialities
Cache locality optimization is an efficient way for reducing the idle time of modern processors in waiting for needed data. This kind of optimization can be achieved either on the...
Jie Tao, Wolfgang Karl