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» A Model of Tolerance
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DC
2007
14 years 9 months ago
Booting clock synchronization in partially synchronous systems with hybrid process and link failures
This paper provides description and analysis of a new clock synchronization algorithm for synchronous and partially synchronous systems with unknown upper and lower bounds on delay...
Josef Widder, Ulrich Schmid
INFOCOM
2009
IEEE
15 years 4 months ago
Time Valid One-Time Signature for Time-Critical Multicast Data Authentication
Abstract—It is challenging to provide authentication to timecritical multicast data, where low end-to-end delay is of crucial importance. Consequently, it requires not only effi...
Qiyan Wang, Himanshu Khurana, Ying Huang, Klara Na...
ISCA
2007
IEEE
120views Hardware» more  ISCA 2007»
15 years 4 months ago
Examining ACE analysis reliability estimates using fault-injection
ACE analysis is a technique to provide an early reliability estimate for microprocessors. ACE analysis couples data from performance models with low level design details to identi...
Nicholas J. Wang, Aqeel Mahesri, Sanjay J. Patel
ISPA
2004
Springer
15 years 3 months ago
Cayley DHTs - A Group-Theoretic Framework for Analyzing DHTs Based on Cayley Graphs
Static DHT topologies influence important features of such DHTs such as scalability, communication load balancing, routing efficiency and fault tolerance. Nevertheless, it is co...
Changtao Qu, Wolfgang Nejdl, Matthias Kriesell
ESORICS
2008
Springer
14 years 11 months ago
Sharemind: A Framework for Fast Privacy-Preserving Computations
Gathering and processing sensitive data is a difficult task. In fact, there is no common recipe for building the necessary information systems. In this paper, we present a provably...
Dan Bogdanov, Sven Laur, Jan Willemson