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» A Model of Tolerance
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TCAD
2010
105views more  TCAD 2010»
14 years 8 months ago
Fault Tolerant Network on Chip Switching With Graceful Performance Degradation
The structural redundancy inherent to on-chip interconnection networks [networks on chip (NoC)] can be exploited by adaptive routing algorithms in order to provide connectivity eve...
Adán Kohler, Gert Schley, Martin Radetzki
DFT
2000
IEEE
104views VLSI» more  DFT 2000»
15 years 6 months ago
How Does Resource Utilization Affect Fault Tolerance?
Many fault-tolerant architectures are based on the single-fault assumption, hence accumulation of dormant faults represents a potential reliability hazard. Based on the example of...
Andreas Steininger, Christoph Scherrer
ICRA
1998
IEEE
100views Robotics» more  ICRA 1998»
15 years 6 months ago
Design for Tolerance of Electro-Mechanical Assemblies
Tolerancing decisions can profoundly impact the quality and cost of electro-mechanical assemblies. Existing approaches to tolerance analysis and synthesis in design entail detailed...
Rachuri Sudarsan, Y. Narahari, Kevin W. Lyons, Ram...
MOBIQUITOUS
2008
IEEE
15 years 8 months ago
Context-aware fault tolerance in migratory services
Mobile ad hoc networks can be leveraged to provide ubiquitous services capable of acquiring, processing, and sharing real-time information from the physical world. Unlike Internet...
Oriana Riva, Josiane Nzouonta, Cristian Borcea
DAC
2009
ACM
16 years 3 months ago
Analysis and mitigation of process variation impacts on Power-Attack Tolerance
Embedded cryptosystems show increased vulnerabilities to implementation attacks such as power analysis. CMOS technology trends are causing increased process variations which impac...
Lang Lin, Wayne P. Burleson