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» A Model of Tolerance
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VLSID
2004
IEEE
117views VLSI» more  VLSID 2004»
15 years 10 months ago
Evaluating the Reliability of Defect-Tolerant Architectures for Nanotechnology with Probabilistic Model Checking
As we move from deep submicron technology to nanotechnology for device manufacture, the need for defect-tolerant architectures is gaining importance. This is because, at the nanos...
Gethin Norman, David Parker, Marta Z. Kwiatkowska,...
PIMRC
2010
IEEE
14 years 7 months ago
How to improve the performance in Delay Tolerant Networks under Manhattan Mobility Model
Delay Tolerant networks (DTNs) are one type of wireless networks where the number of nodes per unit area is small and hence the connectivity between the nodes is intermittent. In t...
Mouna Abdelmoumen, Eya Dhib, Mounir Frikha, Tijani...
IWSEC
2009
Springer
15 years 4 months ago
Tamper-Tolerant Software: Modeling and Implementation
Abstract. Common software-protection systems attempt to detect malicious observation and modification of protected applications. Upon tamper detection, anti-hacking code may produ...
Mariusz H. Jakubowski, Chit Wei Saw, Ramarathnam V...
MOBIHOC
2008
ACM
15 years 9 months ago
Routing performance analysis of human-driven delay tolerant networks using the truncated levy walk model
The routing performance of delay tolerant networks (DTN) is highly correlated with the distribution of inter-contact times (ICT), the time period between two successive contacts o...
Seongik Hong, Injong Rhee, Seong Joon Kim, Kyungha...
FPL
2005
Springer
119views Hardware» more  FPL 2005»
15 years 3 months ago
Yield modelling and Yield Enhancement for FPGAs using Fault Tolerance Schemes
This paper presents a revised model for the yield analysis of FPGA interconnect layers. Based on proven yield models, this work improves the predictions and assumptions of previous...
Nicola Campregher, Peter Y. K. Cheung, George A. C...