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ISSS
2002
IEEE
174views Hardware» more  ISSS 2002»
15 years 4 months ago
A Run-Time Word-Level Reconfigurable Coarse-Grain Functional Unit for a VLIW Processor
Nowadays, new DSP applications are offering combined and flexible multimedia and telecom services. VLIW processor architectures, which include dedicated but inflexible functional ...
Carles Rodoreda Sala, Natalino G. Busá
ARC
2007
Springer
150views Hardware» more  ARC 2007»
15 years 3 months ago
MT-ADRES: Multithreading on Coarse-Grained Reconfigurable Architecture
The coarse-grained reconfigurable architecture ADRES (Architecture for Dynamically Reconfigurable Embedded Systems) and its compiler offer high instruction-level parallelism (ILP)...
Kehuai Wu, Andreas Kanstein, Jan Madsen, Mladen Be...
ECBS
1999
IEEE
171views Hardware» more  ECBS 1999»
15 years 4 months ago
Metamodeling - Rapid Design and Evolution of Domain-Specific Modeling Environments
Model integrated computing (MIC) is gaining increased attention as an effective and efficient method for developing, maintaining, and evolving large-scale, domain-specific softwar...
Greg Nordstrom, Janos Sztipanovits, Gabor Karsai, ...
ISCAS
2005
IEEE
182views Hardware» more  ISCAS 2005»
15 years 5 months ago
A new reconfigurable modem architecture for 3G multi-standard wireless communication systems
– The trend in communication systems is towards more rapidly changing specifications with shorter time intervals between updates of existing standards. This results in a coexiste...
Jung-Ho Kim, Dong Sam Ha, Jeffrey H. Reed
FCCM
1998
IEEE
148views VLSI» more  FCCM 1998»
15 years 4 months ago
JHDL - An HDL for Reconfigurable Systems
JHDL is a design tool for reconfigurable systems that allows designers to express circuit organizations that dynamically change over time in a natural way, using only standard pro...
Peter Bellows, Brad L. Hutchings