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ERSA
2007
177views Hardware» more  ERSA 2007»
15 years 1 months ago
Energy-Aware System Synthesis for Reconfigurable Chip Multiprocessors
- Even though state-of-the-art FPGAs present new opportunities in exploring low-cost high-performance architectures for floating-point scientific applications, they also pose serio...
Xiaofang Wang, Sotirios G. Ziavras, Jie Hu
IJES
2008
130views more  IJES 2008»
14 years 11 months ago
Deriving efficient control in Process Networks with Compaan/Laura
: At Leiden Embedded Research Center (LERC), we are building a tool chain called Compaan/Laura that allows us to map rapidly and efficiently signal processing applications written ...
Steven Derrien, Alexandru Turjan, Claudiu Zissules...
FPL
2008
Springer
112views Hardware» more  FPL 2008»
15 years 1 months ago
Fault tolerant methods for reliability in FPGAs
Reliability and process variability are serious issues for FPGAs in the future. Fortunately FPGAs have the ability to reconfigure in the field and at runtime, thus providing oppor...
Edward A. Stott, N. Pete Sedcole, Peter Y. K. Cheu...
MICRO
2000
IEEE
72views Hardware» more  MICRO 2000»
14 years 11 months ago
PipeRench implementation of the instruction path coprocessor
This paper demonstrates how an Instruction Path Coprocessor (I-COP) can be efficiently implemented using the PipeRench reconfigurable architecture. An I-COP is a programmable on-c...
Yuan C. Chou, Pazhani Pillai, Herman Schmit, John ...
IPPS
2010
IEEE
14 years 9 months ago
Towards dynamic reconfigurable load-balancing for hybrid desktop platforms
s the Pus using the OpenCL API as the platform independent programming model. It has the proposal to extend OpenCL with a module that schedule and balance the workload over the CPU...
Alécio Pedro Delazari Binotto, Carlos Eduar...