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CDES
2006
184views Hardware» more  CDES 2006»
15 years 1 months ago
Compilation for Future Nanocomputer Architectures
Compilation has a long history of translating a programmer's human-readable code into machine instructions designed to make good use of a specific target computer. In this pa...
Thomas P. Way
FCCM
2007
IEEE
122views VLSI» more  FCCM 2007»
15 years 3 months ago
Reconfigurable Computing Cluster (RCC) Project: Investigating the Feasibility of FPGA-Based Petascale Computing
While medium- and large-sized computing centers have increasingly relied on clusters of commodity PC hardware to provide cost-effective capacity and capability, it is not clear th...
Ron Sass, William V. Kritikos, Andrew G. Schmidt, ...
CODES
2006
IEEE
15 years 1 months ago
Architectural support for safe software execution on embedded processors
The lack of memory safety in many popular programming languages, including C and C++, has been a cause for great concern in the realm of software reliability, verification, and mo...
Divya Arora, Anand Raghunathan, Srivaths Ravi, Nir...
IPPS
2010
IEEE
14 years 9 months ago
Structuring the execution of OpenMP applications for multicore architectures
Abstract--The now commonplace multi-core chips have introduced, by design, a deep hierarchy of memory and cache banks within parallel computers as a tradeoff between the user frien...
François Broquedis, Olivier Aumage, Brice G...
MAM
2006
78views more  MAM 2006»
14 years 11 months ago
Operating system power minimization through run-time processor resource adaptation
The increasingly constrained power budget of today's microprocessor has resulted in a situation where power savings of all components in a system have to be taken into consid...
Tao Li, Lizy Kurian John