The wire sizing problem under inequality Elmore delay constraints is known to be posynomial, hence convex under an exponential variable-transformation. There are formal methods fo...
Typically,cell parameterssuch as the pin-to-pinintrinsicdelays, load-dependentcoe cients,andinputpin capacitanceshavedifferent values for rising and falling signals. The performan...
This paper presents a novel approach for post-mapping optimization. We exploit the concept of generalized matching, a technique that nds symbolically all possible matching assignm...
Process variation has become a major concern in the design of many nanometer circuits, including interconnect pipelines. This paper develops closed-form models to predict the dela...
It has become clear that on-chip storage is an essential component of high-density FPGAs. These arrays were originally intended to implement storage, but recent work has shown tha...