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» A Network Congestion-Aware Memory Controller
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ISPASS
2009
IEEE
15 years 6 months ago
GARNET: A detailed on-chip network model inside a full-system simulator
Until very recently, microprocessor designs were computation-centric. On-chip communication was frequently ignored. This was because of fast, single-cycle on-chip communication. T...
Niket Agarwal, Tushar Krishna, Li-Shiuan Peh, Nira...
ANCS
2007
ACM
15 years 3 months ago
Towards high-performance flow-level packet processing on multi-core network processors
There is a growing interest in designing high-performance network devices to perform packet processing at flow level. Applications such as stateful access control, deep inspection...
Yaxuan Qi, Bo Xu, Fei He, Baohua Yang, Jianming Yu...
VLSID
2001
IEEE
144views VLSI» more  VLSID 2001»
16 years 3 days ago
Next Generation Network Processors
Networking hardware manufacturers face the dual demands of supporting ever increasing bandwidth requirements, while also delivering new features, such as the ability to implement ...
Deepak Kataria
DIS
2009
Springer
15 years 6 months ago
CHRONICLE: A Two-Stage Density-Based Clustering Algorithm for Dynamic Networks
Abstract. Information networks, such as social networks and that extracted from bibliographic data, are changing dynamically over time. It is crucial to discover time-evolving comm...
Min-Soo Kim 0002, Jiawei Han
AINA
2008
IEEE
15 years 6 months ago
WS-BPEL Process Compiler for Resource-Constrained Embedded Systems
Process management and workflow systems play an important role in the composition of services in business as well as automation environments. Processes are designed using tools a...
Hendrik Bohn, Andreas Bobek, Frank Golatowski