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» A Network Congestion-Aware Memory Controller
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93
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MICRO
2009
IEEE
147views Hardware» more  MICRO 2009»
15 years 4 months ago
Complexity effective memory access scheduling for many-core accelerator architectures
Modern DRAM systems rely on memory controllers that employ out-of-order scheduling to maximize row access locality and bank-level parallelism, which in turn maximizes DRAM bandwid...
George L. Yuan, Ali Bakhoda, Tor M. Aamodt
ICC
2008
IEEE
176views Communications» more  ICC 2008»
15 years 4 months ago
Reliable Transport with Memory Consideration in Wireless Sensor Networks
—Wireless sensor networks are often composed of resource-constrained sensor nodes with limited memory space, computational capacity and communication range. The links in WSN are ...
Hongchao Zhou, Xiaohong Guan, Chengjie Wu
NCA
2006
IEEE
15 years 3 months ago
A Primary-Backup Protocol for In-Memory Database Replication
The paper presents a primary-backup protocol to manage replicated in-memory database systems (IMDBs). The protocol exploits two features of IMDBs: coarse-grain concurrency control...
Lásaro J. Camargos, Fernando Pedone, Rodrig...
88
Voted
ESTIMEDIA
2007
Springer
15 years 3 months ago
Network Calculus Applied to Verification of Memory Access Performance in SoCs
SoCs for multimedia applications typically use only one port to off-chip DRAM for cost reasons. The sharing of interconnect and the off-chip DRAM port by several IP blocks makes t...
Tomas Henriksson, Pieter van der Wolf, Axel Jantsc...
99
Voted
GECCO
2007
Springer
217views Optimization» more  GECCO 2007»
14 years 11 months ago
A quantitative analysis of memory requirement and generalization performance for robotic tasks
In autonomous agent systems, memory is an important element to handle agent behaviors appropriately. We present the analysis of memory requirements for robotic tasks including wal...
DaeEun Kim