238 search results - page 7 / 48 » A Network Congestion-Aware Memory Controller |
IPPS
2000
IEEE
15 years 1 months ago
2000
IEEE
The Simultaneous Optical Multiprocessor Exchange Bus (SOME-Bus) is a low-latency, high-bandwidth interconnection network which directly links arbitrary pairs of processor nodes wit...
ICS
2003
Tsinghua U.
15 years 2 months ago
2003
Tsinghua U.
Recent work in low-latency, high-bandwidth communication systems has resulted in building user–level Network InControllers (NICs) and communication abstractions that support dir...
72
Voted
ISCA
1996
IEEE
15 years 1 months ago
1996
IEEE
Historically, processor accesses to memory-mapped device registers have been marked uncachable to insure their visibility to the device. The ubiquity of snooping cache coherence, ...
77
Voted
SSS
2010
Springer
14 years 8 months ago
2010
Springer
Abstract. Transformations from shared memory model to wireless sensor networks (WSNs) quickly become inefficient in the presence of prevalent message losses in WSNs, and this prohi...
DSN
2006
IEEE
15 years 3 months ago
2006
IEEE
Embedded control systems consist of multiple components with different criticality levels interacting with each other. For example, in a passenger jet, the navigation system inter...