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» A Network on Chip Architecture and Design Methodology
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CODES
2001
IEEE
15 years 3 months ago
Hardware/software partitioning of embedded system in OCAPI-xl
The implementation of embedded networked appliances requires a mix of processor cores and HW accelerators on a single chip. When designing such complex and heterogeneous SoCs, the...
Geert Vanmeerbeeck, Patrick Schaumont, Serge Verna...
ISCA
2007
IEEE
106views Hardware» more  ISCA 2007»
15 years 6 months ago
Architectural implications of brick and mortar silicon manufacturing
We introduce a novel chip fabrication technique called “brick and mortar”, in which chips are made from small, pre-fabricated ASIC bricks and bonded in a designer-specified a...
Martha Mercaldi Kim, Mojtaba Mehrara, Mark Oskin, ...
FCCM
2007
IEEE
111views VLSI» more  FCCM 2007»
15 years 6 months ago
A Structural Object Programming Model, Architecture, Chip and Tools for Reconfigurable Computing
A new platform for reconfigurable computing has an object-based programming model, with architecture, silicon and tools designed to faithfully realize this model. The platform is ...
Michael Butts, Anthony Mark Jones, Paul Wasson
VLSID
2006
IEEE
192views VLSI» more  VLSID 2006»
15 years 5 months ago
Beyond RTL: Advanced Digital System Design
This tutorial focuses on advanced techniques to cope with the complexity of designing modern digital chips which are complete systems often containing multiple processors, complex...
Shiv Tasker, Rishiyur S. Nikhil
ICCAD
2003
IEEE
127views Hardware» more  ICCAD 2003»
15 years 8 months ago
A Probabilistic-Based Design Methodology for Nanoscale Computation
As current silicon-based techniques fast approach their practical limits, the investigation of nanoscale electronics, devices and system architectures becomes a central research p...
R. Iris Bahar, Joseph L. Mundy, Jie Chen